This invention relates to semiconductor device, and in particular, to a vertical MOS semiconductor device where the source, channel and drain thereof are perpendicularly arranged on an SOI substrate. This invention also relates to a method of manufacturing such a vertical MOS semiconductor device.
As a semiconductor device for realizing an increased integration and an increased high speed performance, a MOS semiconductor device which is formed on an SOI (Semiconductor On Insulator) has been known.
FIG. 6 shows a MOS semiconductor device of lateral structure wherein an element substrate (P-type Si) 22 is superimposed via an SiO.sub.2 insulating layer 21 on a supporting substrate 20 of P-type Si. A source 23, a channel 24 and a drain 25 are respectively formed in this element substrate 22, and a gate electrode 27 is formed over the channel 24 with a gate insulating layer 26 being interposed therebetween.
FIG. 7 shows a semiconductor device of vertical structure which is disclosed in Japanese Patent Unexamined Publication H/5-41521 and wherein a supporting substrate 28 is superimposed on an element substrate 29 in which a drain 30, a channel 31 and a source 32 are arranged vertically, i.e. in a direction perpendicular to the element substrate 29. A gate electrode 34 is arranged beside these regions 30, 31 and 32 with a gate insulating layer 33 being interposed therebetween. The gate electrode 34, the drain 30, the channel 31 and the source 32 are electrically isolated by an insulating layer 35 formed around them. In this FIG. 7, reference numeral 36 denotes a source wiring, while 37 denotes a gate wiring and 38 denotes a drain wiring.
The SOI structure shown in FIG. 6 is advantageous in the respect of achieving an increased high-speed of performance, since the electric field in the inversion layer is weakened in the direction perpendicular to the surface of substrate, thereby making it possible to enhance the mobility of carriers. However, since the source 23, channel 24 and drain 25 are arranged laterally in this MOS structure, it is accompanied with a problem that the integration degree of elements would be limited.
In the case of the conventional semiconductor device of vertical structure shown in FIG. 7, there are also problems that, since the element substrate 29 is designed to be superimposed on the supporting substrate 28, the manufacturing process thereof becomes complicated thus increasing the manufacturing cost, and at the same time, a parasitic bipolar transistor of P-N-P constituted by the element substrate (P) 29, the supporting substrate (P) 28 and the drain wiring (N) 38 is caused to be formed, in addition to the essential MOS transistor constituted by the source (N) 32, the channel (P) 31 and the drain (N) 30, thus instabilizing the performance of the resultant semiconductor device.